table of Contents
Concurrent programming - visibility, atomic and orderliness issues: Bug concurrent programming source
Concurrent programming Beauty Series catalog: https://www.cnblogs.com/binarylei/p/9569428.html
This is the first concurrent programming, describes why concurrent programming, and analysis of the root causes of the problem of concurrent programming - visibility, atomicity and ordering three areas. The next chapter we will continue to analyze how the JVM is to solve these three problems.
1. concurrent program behind the scenes story
Why learn concurrent programming, I think the following reasons:
- CPU, memory, hard drives and other I / O devices, the speed difference on the ground in heaven one day a year.
- The arrival of multi-core era, but also to make full use of CPU.
- To fully a CPU, a cache is introduced, CPU time, sheet, compiler optimization mechanisms. However, these techniques at the same time solve the problem, it also brings security thread. So while the use of a technology, it must be clear what caused the problem is and how to avoid.
1.1 I / O device performance Competition
Over the years, our CPU, memory, hard drives and other I / O devices are constantly iteration, constantly moving in a faster direction. However, in this process of rapid development, there is a core contradiction has always existed, is the speed difference between the three.
- CPU and memory speed difference can be vividly described as: CPU sky day, the memory is on the ground a year.
- Memory and I / O devices, the speed difference is even greater: Memory is in heaven one day, I / O devices are on the ground a decade.
Description: From the chart, we can clearly see, the closer the faster CPU access, but capacity is smaller. Our CPU as a unit, so common I / O device speeds are as follows (we only need to focus on differences in different I / O devices magnitude, do not focus on absolute values):
| IO device | delay | bandwidth | capacity |
|---|---|---|---|
| CPU | 1 | -- | -- |
| Cache (L1-L2-L3) | 0.5~15ns | 2 ~ 60GB / s | 1M |
| RAM | 30~100ns | 2~12GB/s | 32GB~256GB |
| SSD hard drive | 10us~1ns | 50MB~12GB/s | > 1T |
| Mechanical hard drive | 5ms~2ms | 50MB~200MB/s | > 1T |
| NIC | 100us~1ms | 10MB~10GB/s | -- |
1.2 visibility, atomicity, ordering problem
CPU execution often need access memory, some also access the hard disk, according to the bucket theory (a bucket can be How much water depends on its shortest piece of wood), the overall performance of the program depends on the slowest operations - read and write I / O devices, that unilateral improve CPU performance is invalid. To the rational use of CPU performance, balancing speed difference between these three, computer architecture, operating systems, compilers have contributed, mainly reflected in:
- Visibility : the CPU increases the cache to balance and memory speed difference. But the cache also brings visibility problems.
- Atomicity : operating system adds processes, threads, CPU time division multiplexed, and thus the speed difference equalization CPU and I / O devices. But it also brings thread switch atomic issues.
- Ordering : the compiler optimization instruction execution order, so that the buffer can be more rational use. But the compiler optimization can also bring order issues.
2. Visibility
A thread of shared variables modified, another thread can immediately see, we call visibility . CPU cache leads to visibility problems in Java, provides the volatile keyword solve the visibility problem.
First, the cache although efficient, but since it will use the cache of cache inconsistency problems, such as we often use Redis cache. By the same token, CPU cache can lead to inconsistencies, it is visibility. We look at the CPU architecture, detailed cache architecture architecture of the CPU .
Description: "CPU" and "Cache / Memory" interaction is as follows: After receiving the instruction, to find a CPU cache (L1 Cache), however, due to the smaller capacity of the buffer, it can not always hit. Then CPU will continue to look for second-level cache, and so on: L1 Cache -> L2 Cache -> L3 Cache -> RAM -> 硬盘.
If the single-core era, all the instructions are running on the same CPU, not inconsistent caching problems. But the core multiple times, the operation is thread A cache on the CPU-1, and the thread B is a cache operation on the CPU-2. Obviously, this time operation of the variable A thread for thread B does not have the visibility.
Visibility will issue in the following example.
Description: In this example, because the thread B stop the thread A, directly call threadA.stop () will deadlock and other issues. It is usually to stop the thread, often running identifies threads are running with a marker, when we want to stop the thread, call the stop method. But after running thread B directly modify variables, this variable may not be immediately synchronized running into main memory, thread A may not read the latest running variable from main memory, thus leading to visibility problems.
3. atomicity
Operating characteristics of one or more of the processes executed by the CPU is not interrupted, we call atomic . CPU is to ensure that the atomic level CPU instruction, rather than the operator of the high-level language. Thread switching led to the atomicity problems in Java, provides keyword synchronized atomic solve the problem.
The operating system allows a process to perform a short time, such as 50 milliseconds, 50 milliseconds after the operating system will re-select a process to execute (we call "task switching"), this 50 millisecond called "CPU time slice."
Earlier operating system based on process scheduling CPU, different processes are not shared memory space, so the process is necessary to do the task switching switch memory-mapped address, and all the threads of a process to create, is a shared memory space, so thread to do the task switching cost is very low. Modern operating systems are based on more lightweight thread scheduling, and now we mentioned "task switching" refer to "thread switch."
Java concurrent programs are based on multi-threaded, naturally it comes to task switching, task switching timing of most of them in the end of the time slice. We are basically using high-level language programming, in a high-level language statements often require multiple CPU instruction is completed. Such as count ++, need at least three CPU instructions.
- Instruction 1: First, the need to count variable from memory into CPU registers;
- Instruction 2: Thereafter, a +1 in a register;
- Instruction 3: Finally, the results are written to memory (write cache mechanism may lead to a CPU cache instead of memory).
Count ++ or in the above example. A and B are two threads simultaneously execute count ++, even count the use of volatile rhetoric, we expect the result value is 2, but it may actually be 1.
Summary: The operating system task switching can occur after any CPU instruction execution is complete, instead of a high-level language statement. CPU can guarantee atomic operations are CPU instruction level, rather than the language of advanced operators, which is contrary to our intuition place. Therefore, many times we need to ensure that atomic operations in high-level language level.
4. orderliness
In order to optimize the performance of compilers, sometimes changing the order of the statements in the program. In Java, provides a happens-before ordering principle to solve the problem.
5. Summary
In the introduction visibility, atomicity, ordering, when specifically mentioned cache visibility problems caused, thread switching atomic issues brought compiler optimization ordering problems caused. In fact, cache, threads, compiler optimization purposes and we write concurrent programs the same purpose, is to improve program performance. But at the same time to solve a technical problem, it will certainly bring another problem, so while the use of a technology, it must be clear what caused the problem is and how to avoid.
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