D触发器的VHDL语言实现

D触发器的VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
entity DFlip is
port
(
	clk,d:in std_logic;
	q:out std_logic;
	nq:out std_logic
);
end DFlip;

architecture one of DFlip is
begin
	process(clk)
		begin
			if clk' event and clk='1' then
				q<=d;
				nq<=not d;
			end if;
	end process;
end;