Handwriting bootloader (handwriting * _ *)

Thinking
1. Off watchdog
2. Set Clock
3. Initialize SDRAM
4. relocation
5. Run main
.text segment code representing
.global _start (global reference numeral represents the global)

Off watchdog
can be adjusted c disable_watch_dag complete address is determined watchdog .... 0x
LDR r0 of, = 0x ... LDR violation assembler instruction
MOV R1, # 0
STR R1, [r0 of]
to set the clock can be used Clock_Init c ()
CLKDIVN define the location of the board
LDR r0 of, = 0x4c00001
MOV R1, # 0x03 0x03 division factor of FCLK //: HCLK: = the PCLK. 1: 2:. 4, HDIVN =. 1, PDIVN. 1 =
STR R1, [r0 of] ASM if c it is a sign of the read chip embedded in the assembly manual adjustment asynchronous mode, according to the specific circumstances of the chip
mrc instruction register ARM processor to transfer data to a register in the coprocessor. If the coprocessor does not successfully perform this operation, the undefined instruction exception interrupt
MCR { } p15, 0, , , {, }
The operation is performed by the coprocessor opcode. For CP15 coprocessor, the Forever 0b000, when When not 0b000, the instruction operation result unpredictable
ARM register as register element, which value is transferred <
Rd> is not a PC, if it is a PC, you instruction operation to the unpredictable results obtained coprocessor register
Coprocessor register as the destination register, which may be numbered C0, C1 .... C15. Additional or the original destination register operand register, used to distinguish the same number of different physical register. When the instruction does not need to provide additional information, will be designated as C0 Otherwise, operating instructions unpredictable results. Provide additional information, for distinguishing with a different number of physical registers. When the instruction to specify additional information omitted Or be specified as 0, otherwise the operation instruction unpredictable results
orr ORR instruction format: ORR {Conditions} {S} destination register operand 1, operand 2
the ORR instructions for performing the logic ring on two operands operation, placing the result in the destination register
operand register should be a 1, operand 2 may be a register, a shift register or an immediate constant.
The instruction set used in certain bits of the operand 1.

MRC instructions in the coprocessor register value is transferred to the ARM processor registers. If the coprocessor does not successfully perform this operation, the undefined instruction exception interrupt

Instruction Example: ORR R0, R0, # 3 ;
the instruction sets bit 0 of R0, the remaining bits remain unchanged.
ORR r0, r0, # 0xD3
0xD3 = 1101 0111
r0 is the 0xD3 for arithmetic or operation, and the result is returned to r0, i.e. the 'bit r0 [7: 6] and bit [4] and bit [2: 0] is set 1