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Foreword:
The previous chapter mainly introduced the concept of the X86 architecture and its advantages and disadvantages. Today we will mainly share with you what the MIPS architecture is and the system classification of the MIPS architecture.
Table of contents:
1. What is the MIPS architecture ? 1. What is the MIPS architecture?
2. Development history
3. Advantages of MIPS architecture 3. Advantages of MIPS architecture
4. System classification of MIPS architecture
Let’s officially start today’s content!
1. What is the MIPS architecture?
MIPS architecture (English: MIPS architecture, the abbreviation of Microprocessor without interlocked piped stages architecture, also a pun on Millions of Instructions Per Second), is a processor architecture that adopts reduced instruction set (RISC).
2. Development history
In 1981, Stanford University professor John Hennessy led his team to implement the first MIPS architecture processor. Their original idea was to increase the speed of CPU operations through instruction pipelines.
In 1984, Professor John Hennessy left Stanford University and founded MIPS Technology Company. In 1985, the R2000 chip was designed, and in 1988, it was improved to the R3000 chip.
In 2002, the Institute of Computing Technology of the Chinese Academy of Sciences began to develop the Loongson processor, which adopted the MIPS architecture. However, it was accused of infringement without the authorization of the MIPS company.
In 2009, the Chinese Academy of Sciences reached a settlement with MIPS and was officially authorized.
3. Advantages of MIPS architecture
1. Small size, low power consumption, low cost and high performance - the most important reasons why ARM is widely used in embedded systems. It
supports Thumb (16-bit)/ARM (32-bit) dual instruction sets, which can be used very well. Compatible with 8-bit/16-bit devices;
2. Extensive use of registers, faster instruction execution;
3. Most data operations are completed in registers;
4. Flexible and simple addressing mode, high execution efficiency;
5. Fixed instruction length;
6. Load_store structure: In RISC, all calculations are required to be completed in registers. The communication between registers and memory is completed by separate instructions. In CSIC, the CPU can directly operate on the memory.
Pipeline processing method
4. System classification of MIPS architecture
32-bit architecture
MIPS32 architecture refreshes the performance standard of 32-bit embedded processors. It is the basis for MIPS Technology's next-generation high-performance MIPS-Based™ processor SoC development blueprint and is upwardly compatible with the MIPS644 64-bit architecture. The MIPS architecture is a leading embedded architecture with a powerful instruction set, scalability from 32-bit to 64-bit, a wide range of software development tools, and support from many MIPS technology company authorized vendors.
The MIPS32 architecture derives privileged mode exception handling and memory management capabilities from the popular R4000/R5000 class of 64-bit processors. It uses a set of registers to reflect the configuration of caches, MMUs, TLBs, and other privileged functions implemented in each core. By standardizing privileged mode and memory management and providing information through configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be executed simultaneously.
The flexibility of its high-performance cache and memory management schemes continues to be a major advantage of the MIPS architecture. The MIPS32 architecture further extends this advantage with well-defined cache control options.
64-bit architecture
MIPS64 architecture refreshes the performance standard for 64-bit MIPS-Based™ embedded processors. It represents the foundation for the next generation of high-performance MIPS processors and is compatible with the MIPS32® 32-bit architecture. The MIPS architecture is a leading embedded architecture with a powerful instruction set, scalability from 32-bit to 64-bit, widely available software development tools, and support from many MIPS technology company authorized vendors. The MIPS64 architecture is based on a fixed-length regularly encoded instruction set and uses a load/store data model. Addresses the growing computing needs of the embedded market with the addition of data streaming and predicated operations. Conditional data movement and data prefetch instructions are standardized to improve system-level data throughput for communications and multimedia applications.
microarchitecture
microMIPS™ is a high-performance code compression technology that integrates 16-bit and 32-bit optimized instructions in a single unified instruction set architecture. It supports MIPS32 and MIPS64 Release 2 architectures and integrates the variable-length recoded MIPS instruction set and new code-size optimized 16-bit and 32-bit instructions to provide high performance and high code density.
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