in conclusion

If you are too lazy to read the article, just look at the summary here:

Symptom: At a low temperature of -40 degrees, the superframe of the 941 will have a black screen on one side, which is normal at room temperature

Cause of the problem: 8155 and 941 are not correctly set to DSI continuous clock mode

Background

In order to meet the requirements of realizing multiple screens on one machine, the current system usually uses superframe/split mode to realize split screens. The general principle is as follows, the SOC side outputs a large image picture (superframe), and then divides it into two left and right pictures on the 941 side, and sends them to the deserializer (948 Des) through port0 (DOUT0) and port1 (DOUT1) respectively via FPD-Link III to achieve the purpose of splitting the screen.

In the automotive industry, the temperature range of equipment components is required to be -40°~120°. Components that can work normally within this temperature range can be called components that meet the requirements of automotive regulations. Similarly, 941, as a car-grade chip, should also be able to meet this requirement.

Symptom

During the test, it is found that before the temperature reaches -40°, the port1 port of all boards will have no image output, while the port0 port output is normal.

After a problem occurs, power on and off the entire board again, but the problem cannot be recovered
After a problem occurs, reset and reinitialize 941 alone, but the problem cannot be restored
After the problem occurs, there is no output regardless of whether the test pattern is written to 941 or 948
After a problem occurs, use the 941 internal clk to generate a test pattern for the 941 reset alone, and the test pattern can be output normally

Analysis

main suspect

From the perspective of DSI signal transmission, the entire transmission chain is divided into the following parts:

8155 → 941
941 internal
941 → 948

As for doubt 1, it is actually easy to rule out, because the output of the system is a superframe, which is a relatively large picture for 8155. If there is a problem with this section, then port0 should not be displayed normally.

For doubt point 2, it mainly involves 941 hardware problems and 941 internal register configuration, so it is the direction of the key investigation

For doubt 3, after cross-validation, it can be directly ruled out (replace port0, port1)

Doubt analysis

Split doubt point 2, which can be roughly divided into:

software direction
- 941 register configuration, the direction of key investigation
hardware direction
- 941 Peripheral hardware problem
  - MODE SEL problem, the hardware engineer has changed various MODEs, but it has no effect, and the problem remains
  - Clock problem, try to use an external crystal oscillator as the clock source, but it cannot match the 941 requirements
- 941 chip itself problem

Comparison of registers before and after the problem

We dumped the entire 941 main register before and after the problem occurred, you can refer to the file port1_after.txt port1_before.txt

The main differences and analysis are as follows:

Part 1

0x0A: This indicates that a CRC error occurred during the I2C read/write process.

0x0C: Indicate that pixel clock is not detect on port1

Part 2

0x58: Indicate that Line Video Error

0x5A:indicate that DSI Frequency is NOT Stable AND No DSI Clock Detected for selected port.

0x5F:Indicate that NO DSI Pixel Frequency.

Part 3

0x6D:BCC error relate to I2C read/write

Part 4

0xC4:

0xC5:

0xC7:

There are No description for these registers on DS90UB941AS-Q1.pdf.

Analysis conclusion

From the register comparison, the problem is more likely to come from the DSI clock.

Review register configuration on 941

Currently, our register configuration for 941 is as follows:

0x01,0x08,      //Disable DSI
0x1E,0x01,      //Select FPD-Link III Port 0
0x4F,0x0C,      //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
0x5B,0x07,      //Force Splitter mode
0x56,0x80,      //Enable Left/Right 3D processing to allow superframe splitting
0x1E,0x02,      //Select FPD-Link III Port 1
0x4F,0x0C,      //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1
0x5B,0x07,      //Force Splitter mode
0x56,0x80,      //Enable Left/Right 3D processing to allow superframe splitting
0x32,0x80,      //Set the line size to 1920(LSB)
0x33,0x07,      //Set the line size to 1920 (MSB)
0x1E,0x01,      //Select FPD-Link III Port 1
0x36,0x00,      //Set crop start X position to 0 (LSB)
0x37,0x80,      //Set crop start X position to 0 (MSB) and enable cropping
0x38,0x7F,      //Set crop stop X position to 1919 (LSB)
0x39,0x07,      //Set crop stop X position to 1919 (MSB)
0x3A,0x00,      //Set crop start Y position to 0 (LSB)
0x3B,0x00,      //Set crop start Y position to 0 (MSB)
0x3C,0xCF,      //Set crop stop Y position to 719 (LSB)
0x3D,0x02,      //Set crop stop Y position to 719 (MSB)
0x1E,0x02,      //Select FPD-Link III Port 1
0x36,0x00,      //Set crop start X position to 0 (LSB)
0x37,0x80,      //Set crop start X position to 0 (MSB) and enable cropping
0x38,0x7F,      //Set crop stop X position to 1919 (LSB)
0x39,0x07,      //Set crop stop X position to 1919 (MSB)
0x3A,0x00,      //Set crop start Y position to 0 (LSB)
0x3B,0x00,      //Set crop start Y position to 0 (MSB)
0x3C,0xCF,      //Set crop stop Y position to 719 (LSB)
0x3D,0x02,      //Set crop stop Y position to 719 (MSB)
0x40,0x04,      //Select DSI Port 0 digital registers
0x41,0x05,      //Select DPHY_SKIP_TIMING register
0x30,0x01,  //Disable port1 remote interrupt due to we use same hw panel for touch interrupt
0x42,0x3C,      //Write TSKIP_CNT value for 300 MHz DSI clock frequency
0x01,0x00,      //enable DSI

The TI team didn't provide a split mode specific configuration, but we found a example code from Splitter Mode Operations With the 941.pdf.

The TI manual does not give details on how to configure the split mode, but you can find an example configuration from the document Splitter Mode Operations With the 941.pdf .

After revisiting our configuration code, we found an obvious problem:

From the description of 0x56:

Currently we are using the DSI reference clock as the clock source of 941, so BRIDGE_CTL:DSI_CONTINUOUS_CLK must be set, but the configuration for 0X4F in the configuration is 0x0c:

But the register description here does not tell us how to set enable DSI CONTINUOUS CLK (is bit 7 = 1 means Continuous clock or bit 7 = 0 means Continuous clock?)

For this reason, we filed a case on e2e.ti.com, and ti also answered our questions in time:

Solution

Set 0X4F register to 0X8C to enable DSI CONTINUOUS CLOCK.

It should be noted that the DSI output on the SOC side must also be set to continuous clock mode. On the 8155, you can confirm by reading the register HWIO_DSI_0_CPHY_MODE_CTRL_DLN0_CONTINUOUS_CLK_MODE_EN_BMSK bit , or you can set sDeviceConfig.bEnableClkLaneHighPwrMode = TRUE in the driver on the QNX side to ensure that the DSI continuous clock output.

The register for the DSI continuous clock on the 8155 is: HWIO_DSI_0_LANE_CTRL_ADDR.

On 8155 android platform or single linux platform, you can enable continuous clock mode by configuring qcom, mdss-dsi-force-clock-lane-hs in dts.

How to confirm whether the clock output by DSI is a continuous clock:

CONTINUOUS CLOCK(probing on DSI0_CLKP)

NON-CONTINUOUS CLOCK sample (probing on DSI0_CLKP)

DS90UB941 low temperature (-40°C) black screen sharing caused by DSI continuous clock and discontinuous clock