For a long time, DFT has been a relatively mysterious position in the digital IC design industry. You say it is important, not all chip design companies have this position, you say it is not important, but after the chip product reaches a certain scale, it is necessary to set up a DFT department.
1. What is DFT?
DFT (Design For Test), the Chinese name is design for testability. To put it simply, it is to solve some of the problems in the post-silicon test link at the chip design stage, improve the testability of the chip after the tape-out, and greatly reduce the cost of testing money and time. The specific operation is to insert some hardware logic in the chip design process, such as inserting scan chains, leading out JTAG debugging interfaces, etc., to increase the controllability and observability of the internal nodes of the circuit, and to achieve the purpose of testing large-scale chips. Although it is a post for testing, it still belongs to the chip design stage in terms of job distribution.
2. What is the daily work content of DFT engineers?
Generally speaking, after receiving the project, the engineers in each position will meet together to determine the DFT Spec, including IP test strategy, Pin Sharing, HT Block division, and Clock design. Then the DFT design is carried out, that is, the sub-modules are inserted into the aforementioned circuits in the design for synthesis, followed by the Scan Chain connection and the insertion of related circuits. The next step is the verification link, using targeted EDA tools for circuit verification. At the same time, it is necessary to cooperate with the backend for physical implementation. This link may undergo multiple circuit adjustments according to different requirements of the backend. When the netlist is finally physically implemented, it is necessary to use tools to run ATPG, generate test vectors and perform gate-level simulation verification. It's not over yet, the most critical step remains. After the chip is produced, it is necessary to carry out pattern bring-up with TE, and assist TE to complete all the debugging work of pattern import and mass production. We can say with certainty that DFT engineers are all-rounders in the design process. At this point, the work of a DFT engineer in the project is considered to be over, and then rush to the next project.
3. Job prospects
Most people have a misunderstanding about DFT positions: only large companies will set up DFT positions. In fact, DFT is only related to the size of the chip. For example, start-up GPUs have DFT positions in small companies, but the requirements for yield are not high. The scarcity of DFT is often not a lack of jobs, but a lack of talents. Compared with the other three directions, it is more difficult to find an excellent DFT engineer.
The salary is not inferior in comparison. A senior DFT engineer (with 5 years of experience) can get a basic monthly salary of 50-80K. If you can lead a team, there is also a monthly salary of 50K for an engineer with 3 years of experience. At present, the IC design industry is under the trend of rapid development. As DFT is a necessary position to control the quality of chips, the demand for DFT talents in enterprises is increasingly strong.
In fact, there are no majors who can directly work in DFT positions as soon as they graduate. They are either trained internally by the company or transferred to other positions as engineers. Various reasons have created the scarcity of DFT engineers, and the corresponding salary is also rising. The general DFT job offers for fresh masters are 35W-40W.
If you are facing the choice of entering/changing IC, and you are still not sure about the positions in various directions, you are not interested in code, and you don’t want to be a back-end, then you might as well consider DFT, which is also a job choice that can go a long way and is worth fighting for.
If you want to know more about DFT's entry threshold, entry requirements, things to learn, employment salary, etc., you can click below to learn more.
Let’s put it here: Getting started with DFT
STA in DFT
EDT overview
