When doing synthesis, I often mention the wire loadmodel, but I don’t know much about it. I only know that it is a model method for roughly estimating the line delay for processes above 0.18um .
Recently, I had time to read the primepower documentation, and I finally got some understanding.
The Wireload model is actually a number of fanout-length pairs in the comprehensive library, or a table to find the length according to the fanout.
Latency is for the net. The delay of a signal passing through a net is simply determined by the length of the net.
And each net has a certain number of pins connected to it. The so-called fanout of a net is the number of all pins except the pin driving the net. The wireload model is to estimate the delay generated by a net based on the number of loads driven by a net.
Of course, the table is limited, and it is impossible to cover all fanout values, so sometimes an estimation parameter is provided in the comprehensive library, and the synthesizer generates the length of the net through interpolation and other algorithms based on the actual fanout.
Knowing the length of a net , multiplied by the capacitance per unit length (according to the specific process conditions, also provided by the line load model) , and then the delay caused by it can be estimated according to the capacitance on the net.
For processes above 0.18um, since the line delay accounts for a small proportion of the total delay (including line delay and gate delay), it is acceptable to use the line load model.
For a smaller-sized process, the gate delay is significantly reduced, the proportion of the line delay is increased, and the increase in the integration level has caused the complexity of the wiring. Therefore, the length of a net cannot be determined simply based on its load. This is also the reason why physics synthesis is moving towards the front end.
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