In response to this problem, I think such an explanation should be given, as shown in the figure below:
It needs to be clear that, in the case of ignoring the sub-threshold current of the MOS tube and its internal capacitance, it should be considered that when the gate voltage is lower than the threshold voltage, the switching off of the MOS tube is completed instantaneously. The charging and discharging of the mentioned CMOS inverter are based on the load capacitance CL.
First analyze the process of input In from 1→0, the corresponding time is $t_{pHL}$ ($t_{pLH}$ is defined as the time from low level to high level of output out)
At this time, out is from 0→1, the NMOS transistor is in the off state, and the PMOS transistor is in the on state, which is equivalent to charging the capacitor in the path in the figure below.
Therefore, it is better to understand why the formula of $t_{pLH}$ is:
Secondly, analyze the process of input In from 0→1, the corresponding time is $t_{pHL}$ ($t_{pHL}$ is defined as the time from high level to low level of output out)
At this time, out changes from 1 to 0, the PMOS transistor is in the off state, and the NMOS transistor is in the on state, which is equivalent to discharging the capacitor in this path.
