1. What is the `timescale command?
I believe everyone is familiar with the `timescale command, and has seen it more or less. Most people may be able to use it, but in fact, there are some things that need to be paid attention to when using this common command.
`timescale is a precompiled directive in Verilog syntax, usually used to specify the unit and precision of time in simulation.
2. Usage of `timescale
`timescale contains two parts, time unit and time precision . The format is `timescale timeunit / timeprecision.
timeunit represents the simulation time unit, and timeprecision represents the simulation time precision.
For example: `timescale 1ns/1ps or `timescale 1us/1ns and so on.
Notice:
- The time unit and time precision can only be one of the three integers 1, 10 and 100
- Units can be s, ms, us, ns, ps and fs
- Time precision must be less than or equal to the time unit
Let's look at a simple example to understand the use of `timescale:
`timescale 10 ns / 1 ns //单位10ns，精度1ns
module test;
reg set;
parameter d = 1.6;
initial begin
#1 set = 0; //1*10 ns = 10ns
#d set = 1; //1.6*10ns = 16ns
end
endmodule- The time unit is set to 10ns, and the precision is set to 1ns
- For the first time, assign 0 to set at #1, and the delay time is 10ns at this time, because the time unit is 10ns, and #1 indicates a delay of 1 time unit
- For the second time, assign 1 to set at #d. At this time, the delay time is 16+10ns, because the time unit is 10ns. #d means the delay is 1.6 time units, that is, 16ns.
The simulation waveform is as follows:
The set does not give an initial value, so it is an indeterminate state; it is assigned a value of 0 at 10ns and a value of 1 at 26ns, and the minimum unit of the measurement scale is 1ns, that is, the precision is 1ns. All of the above satisfy the inference.
Through the above example, you can understand the use of time units, but it is impossible to see how the time precision setting affects the delay. Next, we will slightly change the above TB code, as follows:
`timescale 10 ns / 1 ns //单位10ns，精度1ns
module test;
reg set;
parameter d1 = 1.54;
parameter d2 = 1.55;
initial begin
#1 set = 0; //1*10 ns = 10ns
#d1 set = 1; //1.54*10ns = 15.4ns ≈ 15ns(四舍五入)
#d2 set = 0; //1.55*10ns = 15.5ns ≈ 16ns(四舍五入)
end
endmodule- The time unit is set to 10ns, and the precision is set to 1ns
- For the first time, assign 0 to set at #1, and the delay time is 10ns at this time, because the time unit is 10ns, and #1 indicates a delay of 1 time unit
- For the second time, assign 1 to set at #d1. At this time, the delay time is 15+10ns, because the time unit is 10ns. #d1 indicates that the delay is 1.54 time units, that is, 15.4ns. Cannot represent 15.4ns, it will be rounded to 15ns
- For the third time, assign 0 to set at #d2. At this time, the delay time is 16+15+10ns, because the time unit is 10ns. So it cannot represent 15.5ns, it will be rounded to 16ns
The simulation waveform is as follows:
The set does not give an initial value, so it is an indeterminate state; it is assigned a value of 0 at 10ns, a value of 1 at 25ns, and a value of 0 at 41ns, and the minimum unit of the measurement scale is 1ns, that is, the precision is 1ns. All of the above satisfy the inference.
3. Things to pay attention to
The `timescale directive is not difficult to use, but there are some caveats.
3.1. Do not set meaningless high precision
The higher the time precision, the more resources and time the simulation consumes. According to Clifford E. Cummings' article "VERILOG CODING STYLES FOR IMPROVED SIMULATION EFFICIENCY", Section 8, setting `timescale 1ns/1ps consumes resources is set` 256% of the timescale 1ns/1ns, while the simulation takes nearly twice as long.
I often see some codes (in fact, including myself hahaha), it is directly `timescale 1ns/1ps, but in the simulation process, according to the fact, you don't need to see the ps-level results, it is just a picture to save trouble. In the case where the RTL is not very large, its impact is difficult to detect intuitively, but with the complexity and large-scale design, this will undoubtedly become a disaster.
So when writing TB in the future, you might as well ask yourself: "Do you really need such high precision?"
3.2. Pay attention to the compilation order of multiple `timescales
`timescale is a precompiled instruction of Verilog syntax, and precompiled instructions are usually executed sequentially, which means that once `timescale is compiled, it will have an impact on all subsequent simulation time and accuracy until it encounters Another `timescale instruction (that is, the previous instruction is overwritten, re-precompile time and precision) or `resetall instruction (reset all precompiled instructions).
Of course, I still recommend that you use a `timescale command uniformly to facilitate project management and avoid unnecessary trouble.
4, reference
《IEEE Standard for Verilog® Hardware Description Language》
《VERILOG CODING STYLES FOR IMPROVED SIMULATION EFFICIENCY》