Fu Ge Answer 2020-09-28: #福大Architects Daily One Question#
1. Hardware memory barrier X86
sfence: store| The write operation before the sfence instruction must be completed before the write operation after the sfence instruction.
lfence: load | The read operation before the lfence instruction must be completed before the read operation after the lfence instruction.
mfence: modify/mix | The read and write operations before the mfence instruction must be completed before the read and write operations after the mfence instruction.
2. Atomic instructions, such as the "lock …" instruction on x86 is a Full Barrier, which will lock the memory subsystem during execution to ensure the order of execution, even across multiple CPUs. Software Locks usually use memory barriers or atomic instructions to achieve variable visibility and maintain program order.
3. How to regulate the JVM level (JSR133) LoadLoad
barrier:
For such statements Load1; LoadLoad; Load2
, ensure that the data to be read by Load1 is read before the data to be read by Load2 and subsequent read operations are accessed.
StoreStore barrier:
For such statements Store1; StoreStore; Store2,
before Store2 and subsequent write operations are executed, it is ensured that the write operation of Store1 is visible to other processors.
LoadStore barrier:
For such statements Load1; LoadStore; Store2,
before Store2 and subsequent write operations are flushed out, ensure that the data to be read by Load1 has been read.
StoreLoad barrier:
For such statements Store1; StoreLoad; Load2,
before Load2 and all subsequent read operations are executed, it is guaranteed that the write of Store1 is visible to all processors.