In chapters 9.1 and 9.2, we introduced these two registers "SW_MUX_CTL_PAD_XX_XX" and "SW_PAD_CTL_PAD_XX_XX" to configure IO pins. In this chapter, we will learn about the configuration of GPIO functions (GPIO is a multiplexed function of IO pins) . For example, the IO of GPIO1_IO00 can be multiplexed into 9 multiplexing functions such as I2C2_SCL, ENET1_REF_CLK1, GPIO1_IO00, WDOG3_WDOG_B, etc. GPIO1_IO00 is just one of them. Which multiplexing function is configured specifically, you need to look at this IO in our hardware design. Which function is designed. If we use this pin to control the LED light-emitting diode, then our program will configure this IO to GPIO mode, and then we need to configure the GPIO function, we can refer to Chapter 28 of the manual "General Purpose Input /Output (GPIO)". In this chapter we can see the structure of GPIO as shown in Figure 1:
In the above figure, we can see two places marked with red boxes (1, 2), one of which contains two registers. This is the register for configuring IO multiplexing and IO function attributes introduced in Chapter 6.2. The 2 places indicate the registers that need to be configured when IO is used as GPIO (a total of 8): GPIO.DR, GPIO.GDIR, GPIO.PSR, GPIO.ICR1, GPIO.ICR2, GPIO.EDGE_SEL, GPIO. IMR, GPIO.ISR, in the previous chapter 6.2, we introduced that i.MX6 ULL has 5 groups of GPIO, and each group of GPIO has these 8 registers. Let's look at these registers separately:
First, the GPIOx_DR register, as shown in Figure 2. :
This register is a data register, 32 bits, each bit corresponds to a GPIO, when the GPIO is configured to output, write 1 to the corresponding bit, GPIO will output high level, write 0, GPIO will output low level. If the GPIO is set to input, then read the corresponding bit of this register, you can get the corresponding GPIO status (0 or 1).
Then there is the GPIOx_GDIR register, as shown in Figure 3:
This register is also 32 bits, and each bit corresponds to a GPIO. This register is used to set whether the GPIO is input or output. (The corresponding bit is set to 0, the corresponding GPIO is set to input mode; the corresponding bit is set to 1, the corresponding GPIO is configured to output mode).
Then there is the GPIOx_PSR register, as shown in Figure 4:
This register is also 32-bit, and each bit corresponds to a GPIO. This register is used to read the status (high and low level) of the corresponding GPIO.
Then there is the GPIOx_ICR1 register, as shown in Figure 5:
This register is an interrupt control register. Each group of GPIO has up to 32 GPIOs. This register is used to configure the lower 16 GPIOs. This register is 32 bits, and each two bits represent a GPIO. These two bits are used to configure the interrupt trigger mode. ：
00 Low
level trigger 01 High level trigger
10 Rising edge trigger
11 Falling edge trigger
Take GPIO1_IO3 as an example, if it is set to high level trigger, GPIO1.ICR1=1<<6.
Then there is the GPIOx_ICR2 register, as shown in Figure 6:
This register is also an interrupt control register. Each group of GPIO has up to 32 GPIOs. This register is used to configure the high 16 GPIOs. This register is 32 bits, and each two bits represent a GPIO. These two bits are used to configure the interrupt trigger mode ：
00 Low
level trigger 01 High level trigger
10 Rising edge trigger
11 Falling edge trigger
Take GPIO1_IO7 as an example, if it is set to high level trigger, GPIO1.ICR1=1<<2.
Then there is the GPIOx_IMR register, as shown in Figure 7:
This register is an interrupt mask register. Each bit corresponds to a GPIO. If the interrupt of a GPIO is enabled, then set the bit corresponding to this register to 1. If the interrupt of a certain GPIO is disabled, then set the corresponding bit of this register to 0.
Then there is the GPIOx_ISR register, as shown in Figure 8:
This register is an interrupt status register, a total of 32 bits, each corresponding to a gpio, as long as a GPIO interrupt is generated, the corresponding bit will be set to 1, we can read this register to determine whether the GPIO interrupt is generated . When we finish processing the interrupt, we must clear the corresponding interrupt flag bit (like writing 1 to the corresponding bit of the register, that is, to clear the interrupt flag bit).
Then GPIOx_EDGE_SEL, as shown in Figure 9:
This register is used to set the edge interrupt. This register will override the settings of ICR1 and ICR2, and one GPIO corresponds to one bit. The corresponding bit is set to 1, then it is equivalent to setting the corresponding GPIO to be triggered on rising and falling edges (both edges).
So far we have finished introducing all the registers of GPIO.