设计电路有两个投币口（1元和5角），货物2元一件，不设找零。out表示是否提供货物。
设计代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/07/23 11:30:37
// Design Name:
// Module Name: Test1130
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module Test1130(reset,clk,jiao,yuan,out);
input clk,reset,jiao,yuan;
output out;
reg out;
reg [2:0] state;
parameter idle=0,half=1,one=2,one_half=3,two=4;
always @(posedge clk or posedge reset)
if(reset)
begin
out <= 1'b0;
state <= 0;
end
else
case(state)
idle:begin
out<=0;
if(jiao)
state<=half;
else if(yuan)
state=one;
else
state<=idle;
end
half:begin
if(jiao)
state<=one;
else if(yuan)
state=one_half;
else
state<=half;
end
one:begin
if(jiao)
state<=one_half;
else if(yuan)
begin
out<=1;
state=two;
end
else
state<=one;
end
one_half:begin
if(jiao)
begin
out<=1;
state=two;
end
else
state<=one_half;
end
two:begin
out<=0;
state<=idle;
end
default:begin
out<=0;
state<=idle;
end
endcase
endmodule
测试代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/07/23 16:21:33
// Design Name:
// Module Name: Test1621
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module Test1621;
reg reset;
reg clk;
reg jiao;
reg yuan;
wire out;
always begin
#100 clk=1;
#100 clk=0;
end
initial begin
reset=1;
clk=0;
jiao=0;
yuan=0;
#500;
reset=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
end
Test1130 x1(.reset(reset),
.clk(clk),
.jiao(jiao),
.yuan(yuan),
.out(out));
endmodule
仿真波形
更新一下改进版的自动售货机
增设了售货机的找零功能，将货品价格修改为2.5元一件。
设计代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/07/23 11:30:37
// Design Name:
// Module Name: Test1130
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module Test1130(reset,clk,jiao,yuan,out,change);
input clk,reset,jiao,yuan;
output out,change;
reg out;
reg change;
reg [2:0] state;
parameter idle=0,half=1,one=2,one_half=3,two=4,two_half=5,three=6,cha=7;
always @(posedge clk or posedge reset)
if(reset)
begin
out <= 1'b0;
state <= 0;
change<=0;
end
else
case(state)
idle:begin
out<=0;
if(jiao)
state<=half;
else if(yuan)
state=one;
else
state<=idle;
end
half:begin
if(jiao)
state<=one;
else if(yuan)
state=one_half;
else
state<=half;
end
one:begin
if(jiao)
state<=one_half;
else if(yuan)
begin
out<=0;
state=two;
end
else
state<=one;
end
one_half:begin
if(jiao)
begin
out<=0;
state=two;
end
else if(yuan)
begin
out<=1;
state<=idle;
end
else
state<=one_half;
end
two:begin
if(jiao)
begin
out<=1;
state=idle;
end
else if(yuan)
begin
out<=1;
state<=three;
end
end
three:begin
out<=1;
change<=1;
state<=cha;
end
cha:begin
change<=0;
out<=0;
state<=idle;
end
default:begin
out<=0;
state<=idle;
change<=0;
end
endcase
endmodule
测试代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/07/23 16:21:33
// Design Name:
// Module Name: Test1621
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module Test1621;
reg reset;
reg clk;
reg jiao;
reg yuan;
wire out;
wire change;
always begin
#100 clk=1;
#100 clk=0;
end
initial begin
reset=1;
clk=0;
jiao=0;
yuan=0;
#500;
reset=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入一元
repeat(2)@(posedge clk);
#2; yuan=1;
repeat(1)@(posedge clk);
#2; yuan=0;
//投入5角
repeat(2)@(posedge clk);
#2; jiao=1;
repeat(1)@(posedge clk);
#2; jiao=0;
end
Test1130 x1(.reset(reset),
.clk(clk),
.jiao(jiao),
.yuan(yuan),
.out(out),
.change(change));
endmodule
change的指数1表示0.5元。